In recent years, multilayer printed wiring boards have gradually prevailed to meet a decrease in size of and an increase in packaging density on the printed wiring board. Such multilayer printed wiring boards have been used for reductions in weight and size of many portable electronic devices. Requirements for the multilayer printed wiring boards include a further reduction in thickness of the insulating interlayer and a further reduction in weight of the wiring board itself.
To meet such requirements, a method for manufacturing a multilayer printed wiring board by a coreless build-up process has been employed. The coreless build-up process alternately builds up insulating layers and wiring layers without a so-called core substrate into a multilayer. In the coreless build-up process, it has been proposed to use a copper foil provided with a carrier to facilitate separation between the support and the multilayer printed wiring board. For example, Patent Document 1 (JP2005-101137A) discloses a method for manufacturing a package substrate for mounting semiconductor devices, comprising bonding an insulating resin layer to the carrier surface of a copper foil provided with a carrier to form a support and then forming a first wiring conductor adjacent to the extremely-thin copper layer of the copper foil provided with a carrier by a process, for example, photoresist processing, pattern electrolytic copper plating, or resist removal, followed by forming a build-up wiring layer, releasing the supporting substrate provided with a carrier, and removing the extremely-thin copper layer.
Meanwhile, a copper foil provided with a carrier having an extremely-thin copper layer having a thickness of 1 μm or less has been desired to miniaturize the embedded circuit as shown in Patent Document 1. Accordingly, it has been proposed to form an extremely-thin copper layer by vapor deposition to achieve a reduction in thickness of the extremely-thin copper layer. For example, Patent Document 2 (JP4726855B2) discloses a copper foil with a carrier sheet interposed by a bonding interface layer. The bonding interface layer consists of two sublayers, i.e., a metal sublayer (adjacent to the carrier sheet) and a carbon sublayer (adjacent to the extremely-thin copper layer) and the copper foil layer was prepared by forming a first copper layer having a thickness of 10 nm to 300 nm on the bonding interface layer by physical vapor deposition and further forming a second copper layer by electrolysis. This document also discloses that the metal sublayer of the bonding interface layer may be composed of any one of tantalum, niobium, zirconium, nickel, chromium, titanium, iron, silicon, molybdenum, vanadium, and tungsten.
Patent Document 3 (JP4072431) discloses a copper foil provided with a carrier having a surface provided with, in sequence, a chromium release layer, an antidiffusion layer readily absorbable light having wavelengths oscillated by CO2 gas laser, and an electrolytic copper plating layer, wherein the antidiffusion layer is a single-metal layer composed of an element selected from the group consisting of nickel, cobalt, iron, molybdenum, tungsten, aluminum, and phosphorus, or an alloy layer composed of two or more elements selected from the group consisting of nickel, cobalt, iron, chromium, molybdenum, tungsten, copper, aluminum and phosphorus or a metal oxide layer of one or more elements.